Low Jitter Low Power Phase Locked Loops Using Sub - Sampling Phase Detection

A periodic clock signal is required in many ICs. These clocks are for instance used to define the sampling moments in data converters; to up-convert and down-convert the wanted signals in wireless transceivers and to synchronize the data flow in wireline and optical serial data communication links. The clock timing/phase accuracy affects the overall system performance and therefore a clock generator should have low jitter/phase-noise. Moreover, a clock generator is also desired to dissipate low power to save energy. This thesis aims to design a clock generation phase-locked loop (PLL) with low jitter as well as low power. It starts with the classical PLL phase noise and jitter analysis. Different sources of PLL phase noise are identified and analyzed. The overall PLL phase noise and output jitter are calculated and optimization methods are discussed. The scaling of the PLL jitter and power with the input frequency, output frequency and the division ratio N are examined and a benchmark figure-of-merit is proposed to evaluate the overall PLL jitter and power performance. In some applications, e.g. time-interleaved ADCs and image and harmonic rejection radio transceivers, a group of clocks with multiple phases are needed. Two competing techniques to realize such clocks, one based on a shift register (SR) and the other on a delay-locked loop (DLL), are discussed. The relative merits of the two techniques are compared, primarily based on their jitter and power performance. Analysis shows that a SR is not only more flexible, but also almost always generates less jitter than a DLL for a given power, when both are realized with current mode logic. The analytical results are verified with simulation results. To generate high quality multi-phase clocks, both methods need a reference clock with low jitter. Such a reference clock can be generated using a low jitter PLL which is the main topic of this thesis. In a classical PLL, the phase detector (PD), charge pump (CP) and divider noise is multiplied by N due to the existence of the divide-by-N in the feedback path. This is often the bottleneck for low PLL in-band phase noise. This work proposes to use a sub-sampling PLL (SSPLL) architecture to break this bottleneck. The SSPLL exploits a sub-sampling phase detector (SSPD) that directly samples the high frequency VCO output with the low frequency reference clock and converts the VCO phase error into sampled voltage variation. The SSPLL is divider-less in the locked state and thus has no divider noise. Furthermore, analysis shows that the PD and CP noise is not multiplied by N in this PLL, resulting in very low in-band phase noise. To prove the concepts, a fully integrated 2.2 GHz SSPLL is implemented in 0.18-μm CMOS. It achieves -126 dBc/Hz at 200 kHz in-band